Publications

DAC

1. DAC

   MARIO: A Superadditive Multi-Algorithm Interworking Optimization Framework for Analog Circuit Sizing

   Wangzhen Li, Yuan Meng, Ruiyu Lyu, Changhao Yan, Keren Zhu, Zhaori Bi, Dian Zhou, and Xuan Zeng

   In 2025 62nd ACM/IEEE Design Automation Conference (DAC 25), 2025

   Abs

   Numeric optimization methods are widely utilized to tackle complex analog circuit sizing problems, where the challenges include expensive simulations, non-linearity, and high parameter dimensionality. However, the diverse characteristics exhibited by different circuits result in varied optimization landscapes, making it difficult to identify a single algorithm that consistently outperforms others across all problems. This paper proposes MARIO, a multi-algorithm interworking optimization framework that achieves optimization superadditivity based on a pool of member algorithms and a powerful algorithm-interworking protocol. A computing resource reallocation method is proposed, which employs multi-task Gaussian process regression and portfolio optimization techniques, leading to flexible and prudent online adaption of member algorithms. Furthermore, a cooperative local refinement feature is introduced, allowing algorithms to share evaluation data and leverage each other’s strengths for local search. Experimental results on both synthetic benchmarks and real-world analog circuits demonstrate that MARIO surpasses existing algorithm-combining tools and standard optimization methods.

2. DAC

   Look Before You Leap: A Self-Review Bayesian Optimization Method for Constrained High-Dimensional Design Space Exploration

   Xuyang Zhao, Yiyang Zhao, Zheng Wu, Tianning Gao, Zhaori Bi*, Changhao Yan, Dian Zhou, and Xuan Zeng

   In 2025 62nd ACM/IEEE Design Automation Conference (DAC 25), 2025

   Abs

   High-dimensional constrained optimization poses significant challenges in analog circuit design automation, where expensive simulations and complex design spaces hinder efficient exploration. This paper proposes a self-review Bayesian optimization method that integrates a teacher-student paradigm within a local Bayesian optimization framework to reduce model errors and enhance exploration efficiency in constrained high-dimensional design spaces. The method employs deep ensembles for effective constraint handling, enabling reliable identification of feasible regions. Experimental results on both synthetic benchmarks and real-world analog circuits demonstrate that the proposed approach achieves superior performance compared to state-of-the-art methods for constrained high-dimensional design space exploration.

3. DAC

   HiMOSS: A Novel High-Dimensional Multi-Objective Optimization Method via Adaptive Gradient-Based Subspace Sampling for Analog Circuit Sizing

   Tianchen Gu, Ruiyu Lyu, Zhaori Bi*, Changhao Yan, Fan Yang, Dian Zhou, Tao Cui, Xin Liu, Zaikun Zhang, and Xuan Zeng

   In 2024 61th ACM/IEEE Design Automation Conference (DAC 24), 2024

   Abs

   This study presents a novel high-dimensional multi-objective optimization method via adaptive gradient-based subspace sampling for analog circuit sizing. To handle constrained multi-objective optimization, we exploit promising regions from a non-crowded Pareto front, with lightweight Bayesian optimization (BO) based on a novel approximate constrained expected hypervolume improvement. This lightweight BO is computational efficient with constant complexity concerning simulation numbers. To tackle high-dimensional challenges, we reduce the effective dimensionality around promising regions by sampling candidates in an adaptive subspace. The subspace is constructed with gradients and previous success steps with their significance decaying over iterations. The gradients are approximated by sparse regression without additional simulations. The experiments on synthetic benchmarks and analog circuits illustrate advantages of the proposed method over Bayesian and evolutionary baselines.

4. DAC

   EVDMARL: Efficient Value Decomposition-based Multi-Agent Reinforcement Learning with Domain-Randomization for Complex Analog Circuit Design Migration

   Handa Sun, Zhaori Bi*, Wenning Jiang, Ye Lu, Changhao Yan, Fan Yang, Wenchuang Hu, Sheng-Guo Wang, Dian Zhou, and Xuan Zeng

   In 2024 61th ACM/IEEE Design Automation Conference (DAC 24), 2024

   Abs

   Automated analog circuit design migration significantly alleviates the burden on designers in circuit sizing under various operating conditions. Conventional methods model the migration problem as black-box optimization, requiring excessive iterations of costly simulations to converge. Reinforcement learning exhibits significant promise in transfer learning, as it enables the generation of circuits that fulfill specifications efficiently. This paper proposes EVDMARL, a novel value decomposition-based multi-agent reinforcement learning framework that models complex analog circuits and eliminates the need for manually defined specifications of sub-circuits for new operating conditions. Furthermore, domain randomization is incorporated to efficiently generate circuits that meet unforeseen scenarios with minimal simulations. Experimental results on real-world analog circuits demonstrate the effectiveness of the proposed framework for complex analog circuit design migration.

5. DAC

   cVTS: A Constrained Voronoi Tree Search Method for High Dimensional Analog Circuit Synthesis

   Aidong Zhao, Xianan Wang, Zixiao Lin, Zhaori Bi*, Xudong Li, Changhao Yan, Fan Yang, Li Shang, Dian Zhou, and Xuan Zeng

   In 2023 60th ACM/IEEE Design Automation Conference (DAC 23), 2023

   Abs

   A constrained Voronoi tree-based domain decomposition method for high-dimensional Bayesian optimization is proposed to solve large scale analog circuit synthesis problems, which can be formulated as high-dimensional heterogeneous black-box optimization. The hierarchical Voronoi tree progressively breaks down the design space into partitions with implicit performance boundaries such that promising regions are efficiently explored. Combined with a local Bayesian optimization strategy within each partition, the method effectively balances exploration and exploitation in high-dimensional spaces. Experimental results on both synthetic benchmarks and real-world analog circuits demonstrate that the proposed method significantly outperforms state-of-the-art methods in terms of optimization quality and convergence speed.

TCAD

1. TCAD

   VSTherm: A Virtual Path-based Stochastic Solver for Full-Chip Leakage-Aware Nonlinear Thermal Simulation

   Yuan Meng, Zhixuan Dong, Yuyan Wang, Changhao Yan, Zhaori Bi, Keren Zhu, Sheng-Guo Wang, Dian Zhou, and Xuan Zeng

   IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2026

   Abs

   The continuous advancement of semiconductor processes has led to increasingly prominent leakage power issues in integrated circuits (ICs), making leakage-aware nonlinear thermal simulation a critical challenge in modern chip design. Traditional deterministic field solvers provide high accuracy but suffer from significant computational inefficiencies when handling large-scale mesh structures. Conversely, stochastic methods offer rapid computation speeds but are inherently limited to single-point solutions, preventing them from effectively addressing nonlinear thermal problems. To address this challenge, we propose a virtual path-based stochastic solver that enables efficient leakage-aware thermal simulation. The virtual path algorithm decomposes each real path in Brownian motion into virtual paths, extending stochastic solvers from single-point solutions to regional solutions, allowing a stochastic method to achieve full-chip thermal simulation for the first time, thus enabling the handling of nonlinearity. Extensive experimental evaluations demonstrate that our method achieves a speedup of 20.17x to 52.23x compared to the state-of-the-art solver 3D-ICE on 4 GPUs across various scenarios while maintaining comparable accuracy.

2. TCAD

   High-Dimensional Yield Optimization for Analog Circuits via Monte Carlo Tree Search and Self-Regressive Auto-Encoder Promoted Subspace Decomposed Gaussian Process

   Zhaoting Chen, Jianping Guo, Zhaori Bi*, Changhao Yan, Fan Yang, Dian Zhou, and Xuan Zeng

   IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2025

   Abs

   Yield optimization is a critical task in analog circuit design automation, where the goal is to maximize the probability that a circuit meets its performance specifications under process variations. However, the high dimensionality of the design space poses significant challenges for efficient yield optimization. This paper proposes a high-dimensional yield optimization method for analog circuits that combines Monte Carlo tree search (MCTS) with a self-regressive auto-encoder promoted subspace decomposed Gaussian process. The MCTS quickly identifies promising local regions within the design space, while the self-regressive auto-encoder learns a compact latent representation to enable effective subspace decomposition. The subspace decomposed Gaussian process then performs efficient Bayesian optimization within the identified regions. Experimental results on real-world analog circuits demonstrate that the proposed method significantly outperforms state-of-the-art yield optimization approaches in both efficiency and solution quality.

3. TCAD

   Atelier: An Automated Analog Circuit Design Framework via Multiple Large Language Model-based Agents

   Jinyi Shen, Zihao Chen, Ji Zhuang, Jiangli Huang, Fan Yang*, Li Shang, Zhaori Bi*, Changhao Yan, Dian Zhou, and Xuan Zeng*

   IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2025

   Abs

   The design of analog circuits requires substantial domain-specific knowledge and extensive manual effort, yet data scarcity limits the application of machine learning techniques in this field. This paper presents Atelier, a large language model (LLM)-based framework for analog circuit design that integrates general-purpose LLMs with a high-quality, compact knowledge base to fulfill the considerable knowledge requirements, obviating the need for extensive domain-specific training or fine-tuning. The framework comprises several LLM agents, structured in a graph-of-thoughts architecture, with each agent specialized in a distinct task including circuit analysis, topology selection, topology modification, parameter tuning, and design decision. The collaborative multi-agent system, enriched with access to the compact knowledge base and advanced mechanisms such as self-reflection, backtracking, and tool integration, automates the analog circuit design process and significantly enhances design quality and efficiency while ensuring interpretability. Experimental results highlight Atelier’s superiority over state-of-the-art black-box methods, general-purpose LLMs, and LLM-based methods, demonstrating notable improvements in success rates, design quality, and runtime.

4. TCAD

   VTSMOC: An Efficient Voronoi Tree Search Boosted Multi-objective Bayesian Optimization with Constraints for High-dimensional Analog Circuit Synthesis

   Aidong Zhao, Ruiyu Lyu, Xuyang Zhao, Zhaori Bi*, Fan Yang, Changhao Yan, Dian Zhou, Yangfeng Su, and Xuan Zeng

   IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2024

   Abs

   Multi-objective optimization with constraints is an important and practical problem in high-dimensional analog circuit synthesis. This paper proposes VTSMOC, an efficient Voronoi tree search boosted multi-objective Bayesian optimization method with constraints for high-dimensional analog circuit synthesis. VTSMOC decomposes the design space into Voronoi cells, dynamically constructing a hierarchical Voronoi tree through clustering observations with dominance relationships. The hierarchical Voronoi tree progressively partitions the design space to identify promising regions with implicit performance boundaries, enabling efficient exploration of the high-dimensional multi-objective optimization landscape. Combined with a local Bayesian optimization strategy within each partition that accounts for multiple objectives and constraints, the method effectively balances exploration and exploitation. Experimental results on both synthetic benchmarks and real-world analog circuits demonstrate that VTSMOC significantly outperforms state-of-the-art multi-objective optimization methods in terms of optimization quality and convergence speed for high-dimensional constrained analog circuit synthesis.

5. TCAD

   APPLE-DSE: Asynchronous Parallel Pareto Set Learning for Microarchitecture Design Space Exploration

   Xuyang Zhao, Tianning Gao, Zheng Wu, Zhaori Bi*, Changhao Yan, Fan Yang, Sheng-Guo Wang, Dian Zhou, and Xuan Zeng

   IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2024

   Abs

   The synthesizable and parameterizable RISC-V microarchitecture, combined with multi-objective optimization-based design space exploration (DSE), facilitates agile adaptation to various microprocessor designs for customized applications. However, to enhance design quality, DSE must consider both architecture parameters and EDA tool parameters, resulting in exponentially increased optimization complexity with the dimensionality of parameters. Exhaustively exploring the whole design space is impossible, and due to the time-consuming nature of microprocessor simulation, minimizing the number of simulations is imperative. This paper proposes APPLE-DSE, an asynchronous parallel Pareto set learning method for microarchitecture DSE. APPLE-DSE utilizes the Pareto Set Learning (PSL) technique to obtain an approximate Pareto front with a light-weight evaluation. PSL captures the structural characteristics of the Pareto set guided by surrogate models, enabling exploration of any trade-off area in the approximate Pareto set. Employing the Probabilistic Reparameterization (PR) technique, APPLE-DSE adapts PSL to handle discrete variables. Furthermore, APPLE-DSE incorporates a simulation time-aware asynchronous parallel scheduling strategy to further enhance optimization efficiency. Experimental results show that APPLE-DSE achieves a maximum improvement of 16.81% in hypervolume within the same time budget and a 127.73x speedup in algorithm run time per iteration compared to state-of-the-art methods.

6. TCAD

   pPIRW: An Efficient and Accurate Pre-calculation Path Integral Random Walk Solver for Steady-State Thermal Simulation With Robin Boundary Conditions

   Zhixuan Dong, Longlong Yang, Cuiyang Ding, Changhao Yan, Zhaori Bi, Sheng-Guo Wang, Dian Zhou, and Xuan Zeng

   IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2024

   Abs

   Conventional deterministic thermal analysis methods have difficulties in obtaining local temperature solutions efficiently, and the existing stochastic method is inaccurate when dealing with thermal analysis problems involving Robin boundary conditions (BCs). This paper proposes a highly parallelized path integral random walk (PIRW) solver for steady-state thermal analysis with mixed boundary conditions, especially Robin BCs. The rigorous calculation of the local time and the Feynman-Kac functional are adopted to accurately handle Neumann and Robin boundary conditions for the first time. Based on the PIRW, an accurate and microsecond-level pre-calculation PIRW (pPIRW) predictor is proposed, which pre-calculates time-consuming random walks, obtains temperatures by simple vector multiplication, and is suitable for proactive thermal management. Compared with 3D-ICE, the PIRW solver maintains high accuracy with a negligible error within 0.5 degrees Celsius, achieves 136-209x speedup and 8.53-11.1x storage space reduction with all three kinds of boundary conditions. The pPIRW has speed improvement of 2.5e4-6.7e6x and memory reduction of 36.6-42.5x over PIRW without loss of accuracy.

7. TCAD

   ATOM: An Automatic Topology Synthesis Framework for Operational Amplifiers

   Jinyi Shen, Fan Yang, Li Shang, Changhao Yan, Zhaori Bi, Dian Zhou, and Xuan Zeng

   IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2024

   Abs

   Automated topology synthesis of operational amplifiers is a fundamental yet challenging task in analog circuit design automation. The design space for behavior-level opamp topologies involves numerous connections that are difficult to comprehend, and evaluating each topology incurs substantial computational costs. This paper proposes ATOM, an automatic opamp topology synthesis framework that constructs a concise design space for behavior-level opamp topologies consisting of topologies designers can easily understand, and proposes an opamp topology optimization method incorporating freeze-thaw Bayesian optimization that efficiently explores the design space and expedites the evaluation process. Experimental studies demonstrate that ATOM outperforms state-of-the-art topology synthesis methods in terms of success rate and optimization results while reducing the number of required simulations by up to 8.15 times.

8. TCAD

   BBGP-sDFO: Batch Bayesian and Gaussian Process Enhanced Subspace Derivative Free Optimization for High-Dimensional Analog Circuit Synthesis

   Tianchen Gu, Wangzhen Li, Aidong Zhao, Zhaori Bi*, Xudong Li, Fan Yang, Changhao Yan, Wenchuang Hu, Dian Zhou, Tao Cui, and  others

   IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD 24), 2024

   Abs

   High-dimensional analog circuit synthesis is a challenging simulation-expensive optimization problem. This paper proposes BBGP-sDFO, a novel batch Bayesian and Gaussian process enhanced subspace derivative free optimization method to solve high-dimensional and simulation-expensive analog circuit optimization problems. The method includes a batch Bayesian querying strategy for exploring the global design space and a Gaussian process enhanced subspace derivative free optimization method for exploiting promising regions in effective low-dimensional subspace. By combining global exploration with local exploitation in reduced subspaces, BBGP-sDFO efficiently handles the curse of dimensionality while maintaining high optimization quality. Experimental results on both synthetic benchmarks and real-world analog circuits demonstrate that BBGP-sDFO significantly outperforms state-of-the-art methods in terms of optimization efficiency and solution quality for high-dimensional analog circuit synthesis.

9. TCAD

   pNeurFill: Enhanced Neural Network Model-Based Dummy Filling Synthesis With Perimeter Adjustment

   Zhaoting Chen, Junzhe Cai, Changhao Yan, Zhaori Bi*, Yuzhe Ma, Bei Yu, Wenchuang Hu, Dian Zhou, and Xuan Zeng

   IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD 24), 2024

   Abs

   Dummy filling is widely applied to significantly improve the planarity of topographic patterns for the chemical mechanical polishing (CMP) process in VLSI manufacturing, with dummy synthesis serving as the key step to adjust the post-CMP profile height. However, existing dummy synthesis optimization approaches usually fail to balance the filling quality and efficiency. This paper proposes pNeurFill, an enhanced neural network model-based dummy filling synthesis framework with perimeter adjustment, integrated with a multiple starting points-sequential quadratic programming (MSP-SQP) optimization solver. Inside this framework, a full-chip CMP simulator is first migrated to the neural network, achieving 8134x speedup on gradient calculation by backward propagation. An improved version with perimeter adjustment (pNeurFill) is further implemented to alleviate the post-CMP height variation caused by dummy perimeter. The extra perimeter adjustment strategy in pNeurFill achieves an average 66.97 Angstrom decrease in height variation and 8.92% quality improvement compared to the baseline NeurFill.

10. TCAD

    Multiagent Based Reinforcement Learning (MA-RL): An Automated Designer for Complex Analog Circuits

    Jiarui Bao, Jinxin Zhang, Zhangcheng Huang, Xingwei Feng, Zhaori Bi, Xuan Zeng, and Ye Lu

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD 24), 2024

    Abs

    Despite the effort of analog circuit design automation, complex analog circuit design still requires extensive manual iterations, making it labor intensive and time-consuming. Recently, reinforcement learning (RL) algorithms have been demonstrated successfully for analog circuit design optimization. However, a robust and highly efficient RL method to design analog circuits with complex design space has not been fully explored yet. In this work, inspired by multiagent planning theory as well as human expert design practice, a multiagent-based RL (MA-RL) framework is proposed. The framework partitions complex analog circuits into several subblocks based on topology information and effectively reduces the complexity of the design search space. It leverages MA-RL for circuit optimization, where each agent corresponds to a single subblock, and the interactions between agents delicately mimic the design tradeoffs between circuit subblocks by human experts. Three different multiagent RL algorithms and corresponding frameworks are introduced and compared to demonstrate the effectiveness of the MA-RL method, with twin-delayed techniques and proximal policy employed to further boost training stability and accomplish higher performances. Experiments on three different complex analog circuit topologies (gain boost amplifier, delay-locked loop, and SAR ADC) and knowledge transfer demonstrate the advantages of the proposed approach.

11. TCAD

    A batched Bayesian optimization approach for analog circuit synthesis via multi-fidelity modeling

    Biao He, Shuhan Zhang, Yifan Wang, Tianning Gao, Fan Yang, Changhao Yan, Dian Zhou, Zhaori Bi*, and Xuan Zeng

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD 23), 2022

    Abs

    Analog circuit design automation and determining design parameters can be formulated as a constrained nonlinear optimization problem, with the design goal of optimizing circuit performances such as power consumption, bandwidth, and gain to meet specifications. This paper proposes a constrained batch Bayesian optimization approach for analog circuit synthesis via multi-fidelity modeling. The batch Bayesian optimization exploits parallel computing and selects promising parameters by multiple acquisition function ensemble. The multi-fidelity model combines information from low and high fidelity simulations to reduce the number of time-consuming high-fidelity simulations required. A well-designed batch selection policy improves hardware resource utilization and convergence rate. Experimental results on real-world analog circuits demonstrate that the proposed method achieves superior optimization results with significantly reduced simulation costs compared to state-of-the-art methods.

12. TCAD

    Smart-MSP: A self-adaptive multiple starting point optimization approach for analog circuit synthesis

    Yishi Yang, Hengliang Zhu, Zhaori Bi, Changhao Yan, Dian Zhou, Yangfeng Su, and Xuan Zeng

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD 17), 2017

    Abs

    Automated analog circuit design is promising for increasing the design productivity and narrowing the time-to-market, but is facing the bottleneck of tremendous design complexity. In this paper, a simulation-based optimization approach named smart-multiple starting point (MSP) is proposed for analog circuit synthesis. The proposed smart-MSP is based on the framework of MSP optimization, which is shown to be much more efficient than other global optimization methods like simulated annealing, genetic algorithm, particle swarm optimization, etc. Efficient techniques including heuristic-biased starting point selection, sparse regression and probabilistic TABU are developed in smart-MSP and make the algorithm self-adaptive by learning from the previous local searches and can efficiently produce optimal results to approximate the global optimum. Experimental results on real-world analog circuits demonstrate that smart-MSP achieves significant improvements in optimization efficiency and solution quality compared to existing approaches.

ICCAD

1. ICCAD

   LCTMwalk: GPU-Accelerated Transient Thermal Simulation for Liquid-Cooled 2.5D/3D ICs via Random Walks on Circuit Networks of Modified Compact Thermal Models

   Zhixuan Dong, Yonghan Luo, Yuan Meng, Changhao Yan, Zhaori Bi, Keren Zhu, Sheng-Guo Wang, Dian Zhou, and Xuan Zeng

   In 2025 IEEE/ACM International Conference On Computer Aided Design (ICCAD 25), 2025

   Abs

   Thermal issues are critical in 2.5D/3D IC design, and liquid cooling provides an effective solution for heat dissipation. Widely used compact thermal models (CTMs) convert chips into circuit networks for fast thermal simulations. However, current matrix-solving acceleration methods for CTM-derived circuits are inadequate for high-speed iterative transient thermal analysis of large-scale liquid-cooled 2.5D/3D ICs during design optimization. In contrast, the random walk method can provide fast solutions for local nodes in large-scale circuit networks, but it is not applicable to the circuit networks of the CTMs with liquid cooling. In this paper, we propose LCTMwalk, a novel GPU-accelerated random walk method for transient thermal analysis of liquid-cooled 2.5D/3D ICs. To enable random walks on the liquid-cooled CTM-derived circuit network, we replace the voltage-controlled current source model with the diode model. Additionally, we improve the transient analysis by using a time-backward random walk with time-domain path reuse. Experimental results show LCTMwalk can solve million-scale cases in only 500 ms, and achieves a 14-22x speedup compared to the state-of-the-art alternating direction implicit (ADI) method with GPU, with high accuracy (error below 1 K compared to 3D-ICE).

2. ICCAD

   NSTherm: An Error-Bounded Network-Stochastic Fusion Thermal Simulator for Geometry-Adaptable Chiplets via Diffeomorphic Mapping and Neural-Guided Variance Reduction

   Yuan Meng, Yuyan Wang, Zhixuan Dong, Yonghan Luo, Changhao Yan, Keren Zhu, Zhaori Bi, Sheng-Guo Wang, Dian Zhou, and Xuan Zeng

   In 2025 IEEE/ACM International Conference On Computer Aided Design (ICCAD 25), 2025

   Abs

   For highly integrated, thermally constrained chiplets, the design process requires iterative shape optimization, making rapid thermal simulation across varying geometries critically important. Existing deterministic approaches, such as COMSOL and HotSpot, require solving large-scale linear systems, incurring expensive computational costs. Stochastic methods suffer from slow convergence, demanding excessive resources for high-precision results. Current neural network (NN)-based methods necessitate retraining upon geometry modifications, limiting adaptability. We enable the fast solution of heat equations for varying geometries and propose a novel solver that integrates operator learning with stochastic methods. By employing diffeomorphic mapping, our approach addresses the challenge of operator networks in handling shape variations. Furthermore, the network’s predictions guide the stochastic method for variance reduction, which extremely accelerates the traditional stochastic method, while the stochastic results provide error guarantees and corrections for the neural network’s outputs. Extensive experiments show that we achieve a speedup of 10.69-23.04x over commercial field solver COMSOL and a speedup of 5.20-11.87x over the traditional stochastic methods.

3. ICCAD

   BAGNet: A Boundary-Aware Graph Neural Network for SRAM Yield Analysis in Post-Layout Simulation

   Haoyang Sang, Changhao Yan, Zhaori Bi*, Keren Zhu, and Xuan Zeng

   In 2025 IEEE/ACM International Conference On Computer Aided Design (ICCAD 25), 2025

   Abs

   SRAM yield analysis in post-layout simulation is critical for ensuring reliable memory designs under process variations. This paper proposes BAGNet, a boundary-aware graph neural network that captures the complex relationships between layout parasitics and SRAM yield metrics. By incorporating boundary-aware attention mechanisms and graph-based representations of the SRAM post-layout structure, BAGNet effectively models the spatial dependencies and boundary effects that significantly impact yield. Experimental results demonstrate that BAGNet achieves highly accurate SRAM yield predictions in post-layout simulation, outperforming existing methods while providing valuable insights for yield-driven design optimization.

4. ICCAD

   Seeing Through Designs: Attention-Based Knowledge Transfer for Preference-Guided Microarchitecture Search

   Yiyang Zhao, Xuyang Zhao, Zhaori Bi*, Ming Zhu, Qiwei Zhan, Keren Zhu, Fan Yang, Changhao Yan, Dian Zhou, and Xuan Zeng

   In 2025 IEEE/ACM International Conference On Computer Aided Design (ICCAD 25), 2025

   Abs

   Modern processor microarchitectures face increasing complexity with larger search spaces and lengthy design-to-silicon validation flows. While reusing design knowledge across architectures offers efficiency gains, the common practice remains specific-architecture search due to discrepancies in power, performance, and area metrics. This paper proposes an attention-based microarchitecture search framework for effective cross-architecture knowledge transfer. A cross-attention network is designed to capture interdependencies between microarchitectural topology and design tool configurations, enabling knowledge adaptation across architectures with minimal fine-tuning. Complemented by an uncertainty-guided optimization strategy, the framework efficiently navigates the design space based on specific user preferences. Experimental results demonstrate that the proposed method achieves significant speedup in microarchitecture design space exploration while maintaining high-quality design outcomes.

5. ICCAD

   Revisiting sensitivity-based analog sizing with derivative-aware Bayesian optimization and error-suppressed adjoint analysis

   Ruiyu Lyu, Aidong Zhao, Yuan Meng, Keren Zhu, Zhaori Bi*, Changhao Yan, Fan Yang, Dian Zhou, and Xuan Zeng

   In 2024 ACM/IEEE International Conference on Computer-Aided Design (ICCAD 24), 2024

   Abs

   Current state-of-the-art analog circuit sizing methods predominantly rely on derivative-free algorithms, but these methods struggle with sample efficiency due to the lack of derivative information, acting as a bottleneck for further advancements. Classic sensitivity analysis computes partial derivatives of circuit performance with respect to design parameters, enabling efficient first-order optimization. However, sensitivity-driven analog sizing has seen limited use due to accumulated numerical errors from nonlinear devices and the complex, non-convex nature of circuit optimization problems, which makes local search methods like gradient descent ineffective for global optimization. This paper proposes DarBO, a derivative-aware Bayesian optimization method that uses derivatives from error-suppressed adjoint sensitivity analysis to improve Gaussian process posteriors in local optimization, enhancing convergence with fewer circuit simulations. Experimental results on both synthetic benchmarks and real-world analog circuits demonstrate the effectiveness of the proposed approach.

6. ICCAD

   AnalogGym: An open and practical testing suite for analog circuit synthesis

   Jintao Li, Haochang Zhi, Ruiyu Lyu, Wangzhen Li, Zhaori Bi*, Keren Zhu, Yanhan Zeng, Weiwei Shan, Changhao Yan, Fan Yang, and  others

   In Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design(ICCAD 24, Invited), 2024

   Abs

   Recent advances in machine learning for automating analog circuit synthesis have been significant, yet challenges remain. A critical gap is the lack of a standardized evaluation framework, compounded by various process design kits, simulation tools, and a limited variety of circuit topologies. These factors hinder direct comparisons and the validation of algorithms. To address these shortcomings, we introduce AnalogGym, an open-source testing suite designed to provide fair and comprehensive evaluations. AnalogGym includes 30 circuit topologies in five categories: sensing front ends, voltage references, low dropout regulators, amplifiers, and phase-locked loops. It supports several technology nodes for academic and commercial applications and is compatible with commercial simulators such as Cadence Spectre, Synopsys HSPICE, and the open-source simulator Ngspice. AnalogGym standardizes the assessment of ML algorithms in analog circuit synthesis and promotes reproducibility with its open datasets and detailed benchmark specifications. We also conduct a comprehensive comparison of various analog sizing methods on the proposed platform.

DATE

1. DATE

   INTO-OA: Interpretable Topology Optimization for Operational Amplifiers

   Jinyi Shen, Fan Yang, Li Shang, Zhaori Bi, Changhao Yan, Dian Zhou, and Xuan Zeng

   In 2025 Design, Automation & Test in Europe Conference (DATE 25), 2025

   Abs

   This paper presents INTO-OA, an interpretable topology optimization method for operational amplifiers (op-amps). We propose a Bayesian optimization-based approach to effectively explore the high-dimensional, discrete topology design space of op-amps. Our method integrates a Gaussian process surrogate model with the Weisfeiler-Lehman graph kernel to extract structural features from a dedicated circuit graph representation. It also employs a candidate generation strategy that combines random sampling with mutation to balance global exploration and local exploitation. Additionally, INTO-OA enhances interpretability by assessing the impact of circuit structures on performance, providing designers with valuable insights into generated topologies and enabling the interpretable refinement of existing designs. Experimental results demonstrate that INTO-OA achieves higher success rates, a 1.84x to 19.10x improvement in op-amp performance, and a 3.20x to 14.33x increase in topology optimization efficiency compared to state-of-the-art methods.

2. DATE

   tSS-BO: Scalable Bayesian Optimization for Analog Circuit Sizing via Truncated Subspace Sampling

   Tianchen Gu, Jiaqi Wang, Zhaori Bi*, Changhao Yan, Fan Yang, Yajie Qin, Tao Cui, and Xuan Zeng

   In 2024 Design, Automation and Test in Europe Conference (DATE 24), 2024

   Abs

   Bayesian optimization (BO) has emerged as a powerful tool for analog circuit sizing, yet its scalability to high-dimensional design spaces remains a critical challenge. This paper proposes tSS-BO, a novel scalable Bayesian optimization method with truncated subspace sampling for large-scale analog circuit sizing. The method addresses the curse of dimensionality by performing optimization in truncated subspaces that capture the most important design variable interactions, thereby reducing the effective dimensionality of the problem while preserving optimization quality. The truncated subspace is adaptively constructed based on observed data to focus the search on the most influential dimensions. Experimental results on both synthetic benchmarks and real-world analog circuits demonstrate that tSS-BO significantly outperforms existing high-dimensional Bayesian optimization methods in terms of optimization efficiency and solution quality.

3. DATE

   Circuits Physics Constrained Predictor of Static IR Drop with Limited Data

   Yuan Meng, Ruiyu Lyu, Zhaori Bi*, Changhao Yan, Fan Yang, Wenchuang Hu, Dian Zhou, and Xuan Zeng

   In 2024 Design, Automation and Test in Europe Conference (DATE 24), 2024

   Abs

   Accurate prediction of static IR drop in power delivery networks (PDN) is crucial for ensuring reliable chip operation. However, existing learning-based methods require large amounts of training data, which is expensive to obtain through detailed simulation. This paper proposes a circuits physics constrained predictor that achieves highly accurate IR drop prediction with limited data. A pyramid scene parsing network with skip-connection architecture is employed to effectively utilize physical information that characterizes IR drop distribution, including current source locations, via locations, and asymmetric topological connections. The skip-connection architecture preserves the positional information of current sources, which often correlates with large IR drop, facilitating the identification of hotspots. Via locations are incorporated to effectively describe the topological connection distance between voltage sources and different nodes in the multi-layer PDN. Experimental results demonstrate that the proposed method achieves high prediction accuracy for PDN of varying scales even with a limited dataset.

ESWEEK

1. ESWEEK

   ROI-HIT: Region of Interest-driven High-dimensional Microarchitecture Design Space Exploration

   Xuyang Zhao, Tianning Gao, Aidong Zhao, Zhaori Bi*, Changhao Yan, Fan Yang, Sheng-Guo Wang, Dian Zhou, and Xuan Zeng

   In 2024 CODES+ISSS (ESWEEK 24), best paper nomination, 2024

   Abs

   Design space exploration of RISC-V processors faces significant challenges due to the vastness of the high-dimensional design space and associated expensive simulation costs. This paper proposes ROI-HIT, a region of interest (ROI)-driven method for high-dimensional microarchitecture design space exploration, which focuses on the promising ROIs to reduce the over-exploration on the huge design space and improve the optimization efficiency. The method identifies and prioritizes regions of interest based on historical evaluation data, enabling efficient allocation of simulation resources to the most promising design configurations. Experimental results on RISC-V BOOM processor design demonstrate that ROI-HIT achieves superior Pareto-optimal designs with significantly fewer simulations compared to state-of-the-art methods.

TODAES

1. TODAES

   CDRPE: A Combined Deep Learning and Self-Attention Enhanced Reinforcement Learning Framework for Automated Compact Model Parameter Extraction

   Gongteng Xiao, Jing Leng, Yijia Shao, Zhenhua Wu, Shisheng Xiong, Zhaori Bi, Xuan Zeng, and Ye Lu

   ACM Transactions on Design Automation of Electronic Systems, 2026

   Abs

   As semiconductor technology node advances, the number of parameters in the modern device compact model increases drastically. Manual extraction of these model parameters becomes not only tedious but also impossible, and the automatic method is strongly desired. Traditional black-box optimization suffers from poor scalability due to the curse of dimensionality, while deep learning-based methods typically require large amounts of training data. To address these challenges, we propose CDRPE: a combined deep learning and self-attention enhanced reinforcement learning framework for automatically extracting a large set of DCM parameters across multiple electrical characteristics. The framework leverages a pre-trained multilayer perceptron to initialize core parameters, incorporates device physics knowledge to guide the search, and employs a self-attention-enhanced RL agent for efficient exploration in high-dimensional parameter spaces. Experimental results on BSIM4, BSIMSOI, and BSIMCMG demonstrate that CDRPE can automatically extract 100 parameters with root-mean-square error below 5% relative to TCAD and silicon data. Compared with existing methods, the proposed framework achieves a 7.7X speed up.

2. TODAES

   Variation-aware Analog Circuit Design via Contextual Modeling and Robust Optimization

   Jiangli Huang, Jinyi Shen, Fan Yang, Li Shang, Zhaori Bi, Changhao Yan, Wenchuang Hu, Dian Zhou, and Xuan Zeng

   ACM Transactions on Design Automation of Electronic Systems, 2025

   Abs

   Robust analog circuit design is becoming increasingly challenging due to process, voltage, and temperature (PVT) variations at advanced technology nodes. In this article, we formulate analog circuit synthesis as a robust optimization problem, and propose a Contextual Robust Optimization (CROZA) method for variation-aware analog circuit design. The proposed method uses a Contextual Gaussian process to model both the design parameters and perturbation parameters, and a hybrid strategy of adversarially robust optimization and stochastically perturbed robust optimization to find robust solutions. Compared to state-of-the-art methods, our proposed approach achieves significant simulation and runtime speedups while delivering superior optimization results.

3. TODAES

   Hierarchical Integration of Reinforcement Learning and Optimization Algorithms for Time-Efficient Design Automation of Complex Analog Circuit

   Xingwei Feng, Yifan Xu, Zhangcheng Huang, Wuyi Xu, Zhaori Bi, Fan Yang, Xuan Zeng, and Ye Lu

   ACM Transactions on Design Automation of Electronic Systems, 2025

   Abs

   Design automation of complex analog circuits (CAC) with multiple sub-blocks is challenging mainly due to large design search space, uncertain intermediate subgoal creation, and lengthy CAC simulation runtime. This paper proposes a hierarchical and heterogeneous integration framework as a fully automated and time-efficient CAC design optimization solution. The framework decomposes CAC into two levels hierarchically and for the first time introduces hierarchical reinforcement learning agents with hindsight and subgoal testing to automate the subgoal creation between these two levels. The subgoal converges to the optimal value through algorithm interactions. At each level, optimization algorithms are integrated to efficiently search the design space within the constraints defined by the hierarchical subgoals. Experimental results on complex analog circuits demonstrate that the proposed framework achieves significant improvements in both design quality and optimization time compared to state-of-the-art methods.

4. TODAES

   D3PBO: Dynamic Domain Decomposition based Parallel Bayesian Optimization for Large-scale Analog Circuit Sizing

   Aidong Zhao, Tianchen Gu, Zhaori Bi*, Fan Yang, Changhao Yan, Xuan Zeng, Zixiao Lin, Wenchuang Hu, and Dian Zhou

   ACM Transactions on Design Automation of Electronic Systems (TODAES 24), 2024

   Abs

   Large-scale analog circuit sizing is a challenging optimization problem due to the high dimensionality and expensive simulation costs. This paper proposes D3PBO, a dynamic domain decomposition-based parallel Bayesian optimization method for large-scale analog circuit sizing. D3PBO introduces the dynamic domain decomposition method based on maximum variance between clusters, where the search space is decomposed into subdomains progressively to limit the maximal number of observations in each domain. The time complexity of D3PBO is constant for each iteration, enabling scalable optimization. Multiple Bayesian optimization instances run in parallel across the decomposed subdomains, efficiently utilizing computational resources while maintaining effective exploration of the design space. Experiments demonstrate that D3PBO obtains better results with significantly less runtime consumption compared to state-of-the-art methods, achieving up to 10x runtime speedup compared to TuRBO with better solutions for circuit optimization experiments.

5. TODAES

   Optimization and quality estimation of circuit design via random region covering method

   Zhaori Bi*, Dian Zhou, Sheng-Guo Wang, and Xuan Zeng

   ACM Transactions on Design Automation of Electronic Systems (TODAES 17), 2017

   Abs

   Analog circuit design optimization can be formulated as a global optimization problem, where the objective is to find optimal design parameters that satisfy performance specifications. This paper proposes a random region covering method for optimization and quality estimation of circuit design. The method introduces multiple random regions to cover the design space and employs local optimization solvers initiated from random starting points within each region to explore the optimization landscape. A quality estimation framework is developed to assess the quality of obtained solutions without exhaustive enumeration, providing statistical guarantees on the optimality of the design. Experimental results on analog circuit design problems demonstrate that the proposed method achieves efficient global optimization with reliable quality estimation, outperforming conventional optimization approaches.

TVLSI

1. TVLSI

   A RISC-V PPA-fusion Cooperative Optimization Framework Based on Hybrid Strategies

   Tianning Gao, Yifan Wang, Ming Zhu, Xiulong Wu, Dian Zhou, and Zhaori Bi*

   IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI 24), 2024

   Abs

   The optimization of RISC-V designs, encompassing both microarchitecture and CAD tool parameters, is a great challenge due to an extensive and high-dimensional search space. To achieve optimal results across various RISC-V designs, this paper proposes a cooperative optimization framework (COF) that integrates multiple black-box optimizers, each specializing in different optimization problems, based on hybrid strategies. The COF introduces the landscape knowledge exchange mechanism (LKEM) to direct the optimizers to share their knowledge of the optimization problem, and employs the dynamic computational resource allocation (DCRA) strategies to dynamically allocate computational resources to the optimizers. By fusing PPA (power, performance, and area) objectives, the framework enables comprehensive cooperative optimization of RISC-V processor designs. Experimental results demonstrate that the proposed framework achieves superior PPA trade-offs compared to state-of-the-art design space exploration methods.

2. TVLSI

   Automated technology migration methodology for mixed-signal circuit based on multistart optimization framework

   Liuxi Qian, Zhaori Bi, Dian Zhou, and Xuan Zeng

   IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI 14), 2014

   Abs

   Technology migration for mixed-signal circuits from one process node to another is a critical but labor-intensive task in the semiconductor industry. This paper presents a hierarchical methodology for efficiently migrating mixed-signal circuit design from one technology node to another, while keeping the same circuit and layout topologies. The multistart global optimization technique is applied to resize the transistor-level block in systematic connection, which provides a good initial point for next system-level refinement. For obtaining a process and parasitic closure solution, both parasitic and process variation effects are explored and used to constrain the schematic migration. A representative mixed-signal system, charge-pump phase-locked loop, is used to validate the proposed methodology. The experimental results show that the proposed methodology efficiently generates quality designs in target technology with much less simulation iterations, when comparing with recent available approaches.

ASP-DAC

1. ASP-DAC

   Synchronous Batch Constrained Multi-Objective Bayesian Optimization for Analog Circuit Sizing

   Xuyang Zhao, Zhaori Bi*, Changhao Yan, Fan Yang, Ye Lu, Dian Zhou, and Xuan Zeng

   In 2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC 24), 2024

   Abs

   For analog circuit sizing, constrained multi-objective optimization is an important and practical problem. With the popularity of multi-core machines and cloud computing, parallel batch computing can significantly improve the efficiency of optimization algorithms. This paper proposes an asynchronous batch constrained multi-objective Bayesian optimization algorithm (ABCMOBO) for analog circuit sizing. The algorithm adopts a dynamic reference point selection on the expected hypervolume improvement acquisition function for constraint handling. To save the time of waiting for all simulations in the same batch to complete, ABCMOBO asynchronously evaluates the next candidate point if there is an idle worker. Experimental results quantitatively demonstrate that the proposed algorithm can reach 3.49 to 8.18x speed-up with comparable optimization results compared to the state-of-the-art asynchronous and synchronous batch multi-objective optimization methods.

2. ASP-DAC

   A Study on Exploring and Exploiting the High-dimensional Design Space for Analog Circuit Design Automation

   Ruiyu Lyu, Yuan Meng, Aidong Zhao, Zhaori Bi*, Keren Zhu, Fan Yang, Changhao Yan, Dian Zhou, and Xuan Zeng

   In 2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC 24), 2024

   Abs

   The escalated intricacy of analog circuits, compounded by the high-dimensional nature of the design space, introduces significant complexities in optimizing circuit performance. Since circuit evaluation through simulation is resource-intensive and time-consuming, the goal is to obtain a feasible design with a decent Figure of Merit (FOM) value within a limited simulation budget. This paper conducts an in-depth review and analysis of cutting-edge exploration and exploitation techniques developed to address the intricacies encountered in analog circuit design automation. We systematically examine methods for navigating the high-dimensional design space, including subspace decomposition, dimensionality reduction, and local search strategies, and discuss their effectiveness in balancing exploration of unknown regions with exploitation of promising areas for efficient analog circuit sizing.

3. ASP-DAC

   A Novel and Efficient Bayesian Optimization Approach for Analog Designs with Multi-Testbench

   Jingyao Zhao, Changhao Yan, Zhaori Bi, Fan Yang, Xuan Zeng, and Dian Zhou

   In 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC 22), 2022

   Abs

   Analog circuits are characterized by various circuit performances obtained from multiple testbenches which need to be simulated independently. This paper proposes a novel and efficient Bayesian optimization approach for analog designs with multi-testbench. Predictive Entropy Search with Constraints (PESC) is applied for selecting the suitable testbench to simulate, and time-weighted PESC (wPESC) is also proposed considering different analysis time. Furthermore, the Feasibility Expected Improvement (FEI) acquisition function for constraints and solving a multi-modal optimal problem of FEI are proposed to improve the efficiency of exploring feasible regions. Experimental results on real-world analog circuits demonstrate that the proposed approach can gain 2.7 to 3.8x speedup compared with the state-of-the-art method, and achieve better optimization results.

ISCAS

1. ISCAS

   HOLMES: Hierarchical Optimization with poLygonal ModEling for Large-Scale AMS Placement

   Guanhua Chen, Yujie Yan, Jiahua Liu, Zecheng Xu, Linxi Qiu, Yumao Wu, Zhiang Wang, Changhao Yan, Zhaori Bi, and Keren Zhu

   In 2026 IEEE International Symposium on Circuits and Systems (ISCAS 26), 2026

   Abs

   Physical placement is a critical determinant of analog/mixed-signal (AMS) circuit performance. For large-scale designs, existing hierarchical methods lose accuracy due to oversimplification of subcircuits, while flat approaches become computationally infeasible for large circuits. In this paper, we propose HOLMES, a hierarchical placement framework that systematically addresses this accuracy-efficiency trade-off. HOLMES maintains hierarchical design representations with tree-based optimization structures and performs bottom-up refinement to model subcircuits using polygonal representations. For device-level optimization, the framework provides a delayed decision strategy that co-optimizes critical parameters such as the number of fingers (NF) in MOS transistors. Experiments show that our framework achieves performance comparable to state-of-the-art methods on smaller circuits while delivering excellent placement quality for large circuits.

2. ISCAS

   Layout-Aware Standard Cell Synthesis via Reparameterization Multi-Task Bayesian Optimization

   Zhouyang Wu, Ruiyu Lyu, Keren Zhu, Zhiang Wang, Zhaori Bi, Changhao Yan, and Xuan Zeng

   In 2026 IEEE International Symposium on Circuits and Systems (ISCAS 26), 2026

   Abs

   Standard cells (SCs) fundamentally influence the power, performance, and area (PPA) of digital integrated circuits. With advances in manufacturing technology and increasing integration density, traditional sequential design flows face two challenges: upstream "optimal designs" diverge from post-layout reality, and isolated design stages restrict the solution space. We introduce LASS, a Layout-Aware Standard Cell Synthesis framework. LASS addresses key challenges through (1) a multitask Gaussian process (MTGP) regression model that captures the correlation between pre- and post-layout simulation results to transfer rich pre-layout data and enhance post-layout modeling under limited data; and (2) a reparameterization-based probabilistic improvement (RePI) acquisition function for efficient exploration in discontinuous design spaces. Experimental results show that LASS optimizes the PPA figure-of-merit (FoM) to 78% in the best case and 84% on average, compared to the X1-driven designs. Moreover, case studies confirm tangible circuit-level performance improvements, with up to 35% delay reduction.

3. ISCAS

   A Batch Bayesian Optimization Approach For Analog Circuit Synthesis Based On Multi-Points Selection Criterion

   Xu Fu, Changhao Yan, Zhaori Bi, Fan Yang, Dian Zhou, and Xuan Zeng

   In 2022 IEEE International Symposium on Circuits and Systems (ISCAS 22), 2022

   Abs

   This paper proposes an efficient batch Bayesian optimization algorithm for analog circuit synthesis based on the multi-points selection criterion. Simplex evolution operator and Niching Migratory Multi-Swarm Optimizer (NMMSO) are used to generate candidates. The multi-point selection criterion is adopted to select multiple points from the candidates for parallel evaluation, which can make full use of the computing resources. The experimental results demonstrate that this method can reduce the simulation time effectively while achieving better optimization results. Compared with the Multi-objective Acquisition function Ensemble (MACE) and the weighted expected improvement based Bayesian optimization (WEIBO), the proposed approach can accelerate the optimization process by up to 3x and 27x respectively.

ISEDA

1. ISEDA

   GPU Acceleration of A High-precision Stochastic Solver for Steady-state Thermal Analysis with Robin Boundary Conditions

   Yonghan Luo, Yuyan Wang, Zhixuan Dong, Changhao Yan, Zhaori Bi, Keren Zhu, Sheng-Guo Wang, and Xuan Zeng

   In 2025 International Symposium of Electronics Design Automation (ISEDA), 2025

   Abs

   Thermal analysis is crucial for modern chip design. The Path Integral Random Walk (PIRW) solver is a high-precision and highly parallel stochastic method-based solver, which is accurate for steady-state thermal analysis with mixed boundary conditions. However, it requires a large number of paths to ensure a result with small variance, as well as massive jump steps to ensure the convergence of the accumulated temperature. This results in limited performance when executed on CPUs. To address these limitations, we have developed a GPU-accelerated implementation of PIRW that capitalizes on the massive parallelism and advanced scheduling capabilities of modern GPUs. Furthermore, by leveraging the algorithm’s inherent characteristics, we have developed a fitting algorithm that substantially reduces the number of path steps required for convergence. The experiment shows that, compared to a multithreaded version on CPU with 80 threads, the PIRW on NVIDIA A800 GPU with step-reducing fitting technology achieves a speed up of 64.1x.

2. ISEDA

   PZTA: Accelerating Analog Circuit Sizing With A Transferable Circuit Theory-Inspired Pole-Zero Transient Assertion System

   Xiaoyu Zhong, Jintao Li, Zhaori Bi, Yun Li, Fan Yang, Xuan Zeng, and Keren Zhu

   In 2025 International Symposium of Electronics Design Automation (ISEDA), 2025
3. ISEDA

   HiRL-DCMPE: A Combined HiMOSS and RL Framework for Device Compact Model Parameter Extraction

   Ziyan Zhou, Gongteng Xiao, Shisheng Xiong, Zhaori Bi, Fan Yang, Xuan Zeng, and Ye Lu

   In 2025 International Symposium of Electronics Design Automation (ISEDA), 2025
4. ISEDA

   Multi-Armed Bandits-Based Exploring and Exploiting the High-Dimensional Design Space for Analog Circuit with Adjoint Sensitivity

   Ruiyu Lyu, Yuan Meng, Zhaori Bi, Keren Zhu, Changhao Yan, Fan Yang, and Xuan Zeng

   In 2025 International Symposium of Electronics Design Automation (ISEDA), 2025
5. ISEDA

   HD-MCTS: An Analog Circuit Optimization Algorithm Based on High-dimensional Monte Carlo Tree Search

   Zhao Yiyang, Lemeng Li, Ruiyu Lyv, Zhaori Bi*, Changhao Yan, and Xuan Zeng

   In 2022 IEEE International Symposium of EDA (ISEDA 24), best paper, 2024

   Abs

   With the development of semiconductor technology, the design of analog circuits still relies heavily on manual effort, creating an urgent need for automated design tools. This paper proposes HD-MCTS, an analog circuit optimization algorithm based on high-dimensional Monte Carlo tree search. The method combines the advantages of Bayesian optimization and dynamic Monte Carlo tree search to obtain the feasible solution space through adaptive clustering, thereby narrowing the search range of the Bayesian optimization algorithm and improving optimization efficiency. For the Ackley test function, low-noise transconductance amplifier and bandgap voltage reference experiments, compared with Trust Region Bayesian Optimization (TuRBO), the optimization outcomes are enhanced by 20.4 percent to 46.5 percent, leading to a speedup of 0.95 to 2.62 times.

6. ISEDA

   High-Dimensional Analog Circuit Sizing via Bayesian Optimization in the Variational Autoencoder Enhanced Latent Space

   Wangzhen Li, Zhaori Bi*, and Xuan Zeng

   In 2022 IEEE International Symposium of EDA (ISEDA 24), 2024

   Abs

   High-dimensional analog circuit sizing is a challenging optimization problem due to the curse of dimensionality and expensive circuit simulations. This paper proposes a method for high-dimensional analog circuit sizing via Bayesian optimization in a variational autoencoder (VAE) enhanced latent space. The VAE is trained on circuit design data to learn a compact, continuous latent representation that captures meaningful relationships between design parameters. Bayesian optimization is then performed in this lower-dimensional latent space, enabling more efficient exploration of the design space. The approach effectively reduces the dimensionality of the optimization problem while preserving the essential structure of the design space, leading to improved optimization efficiency and solution quality for large-scale analog circuit sizing.

7. ISEDA

   Automated Design of Analog Circuits Based on Parallel Trust Region Bayesian Optimization

   Peng Dong, Ruiyu Lyu, Chunxi Wang, Jiale Chen, Linfeng Jiang, Cunqing Lan, Zhaori Bi*, and Changhao Yan

   In 2022 IEEE International Symposium of EDA (ISEDA 24), 2024

   Abs

   Automated analog circuit design requires efficient optimization methods that can handle the complex, multi-dimensional parameter spaces of modern circuits. This paper proposes an automated design approach for analog circuits based on parallel trust region Bayesian optimization. The algorithm operates in parallel on different trust regions, utilizing a Multi-Armed Bandit algorithm for intelligent sampling to accelerate parameter optimization. By maintaining multiple trust regions simultaneously, the method effectively balances local exploitation within promising regions and global exploration of the design space. Circuit experimental results demonstrate the advantages of this algorithm in achieving faster convergence and better optimization outcomes compared to existing approaches.

8. ISEDA

   Topology Optimization of Operational Amplifiers Using A Performance-aware Representation

   Jinyi Shen, Fan Yang, Li Shang, Changhao Yan, Zhaori Bi, Dian Zhou, and Xuan Zeng

   In 2022 IEEE International Symposium of EDA (ISEDA 24), 2024

   Abs

   Automated topology synthesis of operational amplifiers is a fundamental challenge in analog circuit design automation. This paper proposes a performance-aware representation for topology optimization of operational amplifiers that encodes circuit topologies in a way that captures their performance characteristics. The representation enables efficient search over the discrete topology space by embedding performance-relevant structural information, allowing optimization algorithms to effectively navigate the vast space of possible amplifier configurations. Experimental results demonstrate that the proposed performance-aware representation leads to more efficient topology optimization and the discovery of high-quality operational amplifier designs.

9. ISEDA

   On Accelerating Domain-Specific MC-TS with Knowledge Retention and Efficient Parallelization for Logic Optimization

   Cunqing Lan, Xinyao Wang, Zijian Jiang, Hongyang Pan, Keren Zhu, Zhaori Bi, Changhao Yan, and Xuan Zeng

   In 2022 IEEE International Symposium of EDA (ISEDA 24), 2024

   Abs

   Logic synthesis optimization is a critical step in the electronic design automation flow, where the quality of the synthesis recipe significantly impacts the Quality-of-Result (QoR). This paper proposes a method for accelerating domain-specific Monte Carlo tree search (MC-TS) with knowledge retention and efficient parallelization for logic optimization. The approach incorporates a knowledge retention mechanism that preserves and reuses valuable search experiences across different optimization runs, avoiding redundant exploration. Furthermore, an efficient parallelization strategy is designed to enable concurrent evaluation of multiple synthesis recipes, significantly reducing the total optimization time. Experimental results demonstrate that the proposed method achieves superior QoR compared to existing approaches while substantially reducing the computational overhead.

ICICM

1. ICICM

   Cross-Process Bayesian Multi-Objective Collaborative Optimization For Process Migration

   Zixi Guo, Ruiyu Lyu, Zhaori Bi, Changhao Yan, Ming Zhu, Xiulong Wu, and Xuan Zeng

   In 2025 10th International Conference on Integrated Circuits and Microsystems (ICICM), 2025

   Abs

   This paper introduces a cross-process Bayesian multi-objective collaborative optimization framework to address challenges in semiconductor technology migration. We leverage transfer learning within multi-objective Bayesian optimization through Gaussian copula, transforming simulation data into residual observations. By transferring prior knowledge from implemented technologies to advanced processes, we significantly reduce the number of required circuit simulations in newer technologies, effectively optimizing the parameter design space for next-generation processes. Furthermore, we establish Gaussian process regression models that correlate design variables with performance metrics across both advanced and implemented technologies. These models undergo continuous updates during iteration, enabling collaborative optimization throughout the technology migration engineering process.

2. ICICM

   RLMBFF: Multi-bit Flip-Flops Merging using Deep Reinforcement Learning

   Zeqi Chen, Zhaori Bi, Changhao Yan, Ming Zhu, Xiulong Wu, and Xuan Zeng

   In 2025 10th International Conference on Integrated Circuits and Microsystems (ICICM), 2025

   Abs

   Multi-bit flip-flop (MBFF) merging has been proven to be an effective way to save dynamic power and reduce the utilization rate of the chip area. Most of the existing work uses either a clustering method or an analytical way to merge multiple single-bit flip-flops (SBFFs) into MBFFs. In this paper, inspired by the recent success in deep reinforcement learning, we propose a novel MBFF merging method leveraging neural networks. The approach can be divided into two steps: (i) placing MBFFs by a pretrained RL agent, and (ii) mapping the pin pairs of the original SBFF to the MBFF cell. Experimental results show that our method can significantly save power and area, without large perturbations to the timing.

3. ICICM

   A Pipeline-Based Common Framework for Parallel Mixed Signal Simulation

   Longchen Sun, Guangrong Li, Zhenguo Zhao, Xin Huang, Xuan Zeng, Fan Yang, and Zhaori Bi

   In 2025 10th International Conference on Integrated Circuits and Microsystems (ICICM), 2025

   Abs

   A pipeline-based common framework for parallel mixed signal simulation is proposed, which not only provides new perspectives on developing synchronization algorithms but also improves the efficiency of parallel simulation, particularly for mixed signal cases. Implementation of two-stage pipelines is introduced. The efficiency of the two-stage pipeline is compared to a framework for serial mixed signal simulation, showing a significant runtime speedup ratio of 1.74x to 1.84x in simple cases and 3.57x in a more complicated case involving a DAC (digital to analog converter).

MWSCAS

1. MWSCAS

   Analog circuit performance bound estimation based on extreme value theory

   Minghua Li, Zhaori Bi, Dian Zhou, and Xuan Zeng

   In 2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS 15), 2015

   Abs

   Performance bound estimation is an important task in analog circuit design, as it provides designers with critical information about the achievable performance limits under process variations. This paper proposes a novel performance bound estimation method for analog circuits based on extreme value theory. The method generates a generalized extreme value (GEV) distribution of performance parameters through sampling, enabling accurate estimation of the worst-case and best-case performance bounds without exhaustive Monte Carlo simulations. The approach provides a statistically rigorous framework for bounding circuit performance and offers significant computational savings compared to traditional methods.

TMTT

1. TMTT

   An Iterative FEM Solver for IC Electromagnetic Analysis via Hybrid Geometric-Algebraic Partitioning and Neural Network Optimization

   Mingtao Li, Changhao Yan, Tao Cui, Liguo Jiang, Wenliang Dai, Zhaori Bi, Keren Zhu, and Xuan Zeng

   IEEE Transactions on Microwave Theory and Techniques, 2025

   Abs

   In electromagnetic finite element analysis of integrated circuits (ICs), direct solvers face high time and space complexity in large-scale problems, while traditional iterative methods suffer from unstable, unpredictable convergence and require complex manual configuration. In this article, we propose a practical and efficient iterative solver based on the overlapping additive Schwarz (OAS) preconditioner. We propose a hybrid matrix partitioning algorithm, which combines geometric and algebraic partitioning methods to leverage their complementary strengths. Furthermore, we develop a neural network-based evaluation and optimization system to predict the convergence and computational efficiency of candidate configurations, enabling automated selection of the optimal OAS preconditioner. Experimental results show that our solver achieves 100% convergence across all test matrices, while previous OAS-based iterative methods converge for at most 68%. Compared to the industry-standard direct solver PARDISO and the commercial FEM solver ANSYS HFSS, it achieves average speedups of 3.61x and 2.39x, respectively, along with superior parallel scalability.

TED

1. TED

   S3HDBO: Sensitivity-Guided Search Region Scaling High-Dimensional Bayesian Optimization for BSIM-CMG Parameter Extraction

   Ruiyu Lyu, Zhaori Bi, Keren Zhu, Ye Lu, and Xuan Zeng

   IEEE Transactions on Electron Devices, 2026

   Abs

   Developing accurate Berkeley short-channel IGFET model-common multigate (BSIM-CMG) compact models for FinFET and NSFET devices is challenging because of complex short-channel effects. Two primary obstacles arise: first, the exponentially expanding search space resulting from increased parameter counts, and second, the nonlinearities in I-V and C-V curves that dramatically increase extraction complexity and necessitate numerous iterative computations. Recent deep neural network (DNN) approaches show promise for real-time extraction but suffer from significant limitations, requiring extensive training data and demonstrating poor generalization to new scenarios. Optimization methods, particularly Bayesian optimization (BO), have emerged as popular alternatives due to their flexibility and efficiency. However, conventional BO methods face the curse of dimensionality when applied to complex parameter extraction tasks. To overcome these limitations, we introduce sensitivity-guided search region scaling high-dimensional BO (S3HDBO), an advanced BO framework that employs sensitivity-guided search space pruning and scaling, combined with subspace identification via sliced inverse regression (SIR). The experimental results confirm that our method reduces the number of simulations by two orders of magnitude compared to neural network methods while achieving the same level of accuracy, and achieves a speedup ratio of 3.47x-3.91x compared to state-of-the-art optimization methods.

TCPMT

1. TCPMT

   An Accurate and Efficient Stochastic Solver for Transient Thermal Analysis with Mixed Boundary Conditions

   Zhixuan Dong, Yuan Meng, Changhao Yan, Zhaori Bi, Keren Zhu, Sheng-Guo Wang, Dian Zhou, and Xuan Zeng

   IEEE Transactions on Components, Packaging and Manufacturing Technology, 2025

   Abs

   Transient thermal analysis captures the high accuracy and time-varying temperature distribution of chip components. However, during the early thermal design iterations of 3D ICs and chiplets, time-consuming transient thermal simulations lead to prolonged waiting times for engineers. Existing widely adopted deterministic methods or innovative neural network-based methods face significant challenges in reducing the thermal simulation time when geometric structures change iteratively. With prior knowledge of the chip’s regions of interest, localized stochastic methods may present a promising solution. In this work, we propose a novel high-precision and efficient stochastic solver for transient thermal analysis of ICs, based on the probabilistic solution of the heat equation obtained from the Feynman-Kac formula. As a field solver for the heat equation, the proposed method adopts the spacetime walk-on-sphere (WOS) scheme and enhances it with a novel boundary treatment to guarantee the accuracy of addressing mixed boundary conditions, particularly Robin boundary conditions. Experimental results show that the proposed solver maintains high accuracy with average absolute error within 0.27 K and maximum absolute error within 1 K, and achieves a speedup of 26.8-211x at a single point compared to the 3D-ICE simulator of similar accuracy.

ACS AMI

1. ACS AMI

   A Semi-floating Body Memory Featuring Brain-like Behaviors

   Chengjie Tang, Xiaolong Ma, Kang Wang, Fangxuan Yi, Haobo Huang, Weiao Chen, Feige Lou, Shuiyuan Wang, Shiyou Chen, Zengxing Zhang, Zhaori Bi, Zhibo Chen, Wenpeng Liu, Shisheng Xiong, Peng Zhou, and Ye Lu

   ACS Applied Materials & Interfaces, 2025

   Abs

   Innovating electronic devices to mimic human brain behaviors has been a long-standing desire. Here, we present a semi-floating body memory (SFBM) exhibiting various human brain-like memory behaviors. The SFBM is designed similarly to a p-type silicon-on-insulator (SOI) MOSFET, except that a metal/graphene/silicon overlapping heterojunction is formed close to the drain. The proper operation of device terminal bias voltages introduces and modulates the impact ionization at the heterojunction interface and forms an ungated semi-floating body underneath for charge storage, further enabling multiple unique memory behaviors. The SFBM achieves a fresh retention time of about 1 h, 300 times that of the conventional floating body memory. Importantly, the retention time is extended to over a day by the read operation, precisely mimicking the revisitation behavior of human memory. All these brain-like features position the SFBM as a strong candidate for brain-inspired computing units, and a 1T-1S content-addressable memory (CAM) cell is experimentally demonstrated using a minimum number of transistors for future compute-in-memory (CIM) purposes.

Electronics

1. Electronics

   Topology-Aware Admission Control for Dynamic Load Balancing in NUMA-Based Parallel RTL Simulation

   Xin Huang, Guangrong Li, Fan Yang, and Zhaori Bi

   Electronics, 2026

   Abs

   Parallel discrete-event simulation (PDES) of register-transfer-level (RTL) designs on multi-socket NUMA platforms demand dynamic load balancing to mitigate barrier-induced tail latency. However, the ultra-fine event granularity of RTL simulation makes migration cost non-negligible, and the non-uniform memory hierarchy of NUMA turns migration cost into a topology-dependent variable rather than a constant. Existing approaches either ignore this topology dependence or rely on heuristic thresholds that lack theoretical justification. This paper formulates NUMA-aware dynamic load balancing as a constrained optimization problem in which the migration cost is an explicit function of the socket locality between the source and destination cores. We introduce a unified net benefit function that jointly captures the tail-latency reduction, migration overhead, and cache warm-up penalty for migrating a module from one core to another at a given frequency. We implement the proposed topology-aware admission control (TAC) framework in TACVS, our event-driven parallel RTL simulation prototype. Experiments on four open-source RTL designs running on a 2-socket NUMA platform show that TAC reduces the tail-latency ratio by 18.0% on average (up to 28.5%) and improves normalized throughput by 27.1% on average (up to 34.1%) relative to topology-oblivious baselines.

JBHI

1. JBHI

   Learning From Highly Confident Samples for Automatic Knee Osteoarthritis Severity Assessment: Data From the Osteoarthritis Initiative

   Yifan Wang, Zhaori Bi#, Yuxue Xie, Tao Wu, Xuan Zeng, Shuang Chen, and Dian Zhou

   IEEE Journal of Biomedical and Health Informatics (JBHI 21), 2021

   Abs

   Knee osteoarthritis (OA) is a chronic disease that considerably reduces patients’ quality of life. Preventive therapies require early detection and lifetime monitoring of OA progression. In the clinical environment, the severity of OA is classified by the Kellgren and Lawrence (KL) grading system, ranging from KL-0 to KL-4. Recently, deep learning methods were applied to OA severity assessment to improve accuracy and efficiency. However, this task is still challenging due to the ambiguity between adjacent grades, especially in early-stage OA. Targeting the uncertainty in the OA dataset, we propose a novel learning scheme that dynamically separates the data into two sets according to their reliability. Besides, we design a hybrid loss function to help CNN learn from the two sets accordingly. With the proposed approach, we emphasize the typical samples and control the impacts of low confident cases. Our method achieves a mean accuracy of 70.13% on the five-class OA assessment task, which outperforms all other state-of-art methods. Moreover, we design an experiment to validate large-scale automatic data refining during training. The dataset used in this paper was obtained from the Osteoarthritis Initiative.

JTEHM

1. JTEHM

   A practical electronic health record-based dry weight supervision model for hemodialysis patients

   Zhaori Bi, Mengjing Wang, Li Ni, Guoxin Ye, Dian Zhou, Changhao Yan, Xuan Zeng, and Jing Chen

   IEEE Journal of Translational Engineering in Health and Medicine(JTEHM 19), 2019

   Abs

   Dry Weight (DW) is a typical hemodialysis (HD) prescription for End-Stage Renal Disease (ESRD) patients. However, an accurate DW assessment is difficult due to the complication of body components and individual variations. We proposed a time series-based regression method to evaluate the weight fluctuation of HD patients according to Electronic Health Record (EHR). A total of 34 patients with 5100 HD sessions data were selected and partitioned into three groups: HD-stabilized, HD-intolerant, and near-death. Within a 0.5 kg absolute error margin, our model achieved 95.44%, 91.95%, and 83.12% post-dialysis weight prediction accuracies for the three groups respectively. For HD-stabilized patients, the Mean Absolute Error of the proposed method was 0.17 kg. The outcome of this research indicates that the proposed model could potentially automate the clinical weight management for HD patients and aid physicians to monitor and estimate DW.

JMV

1. JMV

   Risk-stratified management of cervical high-grade squamous intraepithelial lesion based on machine learning

   Zhang Lu, Tian Pu, Li Boning, Xu Ling, Qiu Lihua, Bi Zhaori, Chen Limei, and Sui Long

   Journal of Medical Virology, 2024

   Abs

   The concordance rate between conization and colposcopy-directed biopsy (CDB) proven cervical high-grade squamous intraepithelial lesion (HSIL) were 64-85%. We aimed to identify the risk factors associated with pathological upgrading or downgrading after conization in patients with cervical HSIL and to provide risk-stratified management based on a machine learning predictive model. This retrospective study included patients who visited the Obstetrics and Gynecology Hospital of Fudan University from January 1 to December 31, 2019, were diagnosed with cervical HSIL by CDB, and subsequently underwent conization. Machine learning prediction models were established, evaluated, and subsequently verified using external testing data. In total, 1585 patients were included, of whom 65 (4.1%) were upgraded to cervical cancer after conization, 1147 (72.4%) remained having HSIL, and 373 (23.5%) were downgraded to LSIL or below. Among the six machine learning prediction models, the back propagation (BP) neural network model demonstrated the highest and most uniform predictive performance in the downgrading, HSIL, and upgrading groups, with areas under the curve (AUCs) of 0.90, 0.84, and 0.69. In the external testing set, the BP neural network model showed a higher predictive performance than the logistic regression model, with an overall AUC of 0.91. BP neural network prediction model has excellent predictive performance and can be used for the risk stratification of patients with CDB-diagnosed HSIL.

KBPR

1. KBPR

   Modification and validation of the phosphate removal model: a multicenter study

   Weichen Zhang, Qiuna Du, Jing Xiao, Zhaori Bi, Chen Yu, Zhibin Ye, Mengjing Wang, and Jing Chen

   Kidney and Blood Pressure Research, 2021

   Abs

   Our research group has previously reported a noninvasive model that estimates phosphate removal within a 4-h hemodialysis (HD) treatment. The aim of this study was to modify the original model and validate the accuracy of the new model of phosphate removal for HD and hemodiafiltration (HDF) treatment. A total of 109 HD patients from 3 HD centers were enrolled. The actual phosphate removal amount was calculated using the area under the dialysate phosphate concentration time curve. Model modification was executed using second-order multivariable polynomial regression analysis to obtain a new parameter for dialyzer phosphate clearance. Internal validation indicated that the new model was superior to the original model with a significantly smaller bias and higher accuracy. External validation showed that R2, bias, and accuracy were not significantly different than those of internal validation. A new model was generated to quantify phosphate removal by 4-h HD and HDF with a dialyzer surface area of 1.3-1.8 m2. This modified model would contribute to the evaluation of phosphate balance and individualized therapy of hyperphosphatemia.

Renal Failure

1. Renal Failure

   Effects of a high-phosphorus diet on the gut microbiota in CKD rats

   Guoxin Ye, Wei Yang, Zhaori Bi, Liya Huang, and Fang Liu

   Renal Failure, 2021

   Abs

   This study investigated whether high-phosphorus diets alter gut microbiota in healthy rats and chronic kidney disease (CKD) rats. In a 4-week randomized controlled trial, healthy rats and CKD rats were divided into four groups with regular-phosphorus or high-phosphorus diets. Researchers sequenced the V3-V4 region of the 16S rRNA gene to examine microbiota changes. High-phosphorus intervention increased systolic blood pressure and parathyroid hormone in both groups but did not change serum creatinine and 25(OH)D levels. The gut microbiota was significantly altered after intervention with a high-phosphorus diet. A high-phosphorus diet reduced the Shannon index values of gut microbiota in all rats. Some microbial genera were elevated significantly after high-phosphorus dietary intervention, such as Blautia and Allobaculum. High-phosphorus diets were associated with adverse changes in gut microbiota and elevated systolic blood pressure, which may have adverse consequences for long-term health outcomes.

2. Renal Failure

   Dominant factors of the phosphorus regulatory network differ under various dietary phosphate loads in healthy individuals

   Guoxin Ye, Jiaying Zhang, Zhaori Bi, Weichen Zhang, Minmin Zhang, Qian Zhang, Mengjing Wang, and Jing Chen

   Renal Failure, 2021

   Abs

   The purpose of this study was to explore the contribution of each factor of the phosphorus metabolism network following phosphorus diet intervention via Granger causality analysis. Six healthy male volunteers sequentially received regular, low-, and high-phosphorus diets. Blood and urinary samples were collected for measurements of serum levels of phosphate, calcium, PTH, FGF23, BALP, alpha-Klotho, 1,25 D and urinary phosphorus excretion. The alpha-Klotho level had the strongest connection with and played a key role in influencing the other variables during regular phosphorus intake. Under low-phosphorus conditions, serum phosphate affected the other factors the most. After high-phosphorus diet intervention, FGF23 and 1,25 D played a more critical role in active regulation and passive regulation in the Granger causality analysis. Variations in dietary phosphorus intake led to changes in the central factors involved in phosphorus metabolism.

BMC nephrology

1. BMC nephrology

   Higher one-year achievement rate of serum phosphate associated with lower cardiovascular mortality in hemodialysis patients

   Weichen Zhang, Guoxin Ye, Zhaori Bi, Weisheng Chen, Jing Qian, Minmin Zhang, Ding Ding, Mengjing Wang, and Jing Chen

   BMC nephrology, 2021

   Abs

   Estimation of phosphate load in hemodialysis patients is always controversial in clinical practice. The aim of this study was to verify individual achievement rate of serum phosphate as the evaluation of phosphate load through investigating its impact on cardiovascular mortality in hemodialysis patients. This was a single-center, retrospective cohort study. A total of 251 maintenance hemodialysis patients were enrolled. The individual achievement rate of serum phosphate was defined as the times of tests within the target range divided by total times of tests over a period of time. Multivariable Cox analysis showed that one-year serum phosphate achievement rate of 0% and 25% increased the risk of cardiovascular mortality while the achievement rate of 50% and 75% did not, compared to the rate of 100%. Keeping one-year achievement rate of serum phosphate higher than 50% provides significant clinical benefits in reducing cardiovascular mortality.

BMC geriatrics

1. BMC geriatrics

   A parsimonious approach for screening moderate-to-profound hearing loss in a community-dwelling geriatric population based on a decision tree analysis

   Min Zhang, Zhaori Bi#, Xinping Fu, Jiaofeng Wang, Qingwei Ruan, Chao Zhao, Jirong Duan, Xuan Zeng, Dian Zhou, Jie Chen, and  others

   BMC geriatrics, 2019

   Abs

   Hearing loss is one of the most common modifiable factors associated with cognitive and functional decline in geriatric populations. An accurate, easy-to-apply, and inexpensive hearing screening method is needed to detect hearing loss in community-dwelling elderly people. In total, 1793 participants aged 60 years and above were recruited to undertake a standard audiometric air conduction pure tone test at 4 frequencies. The decision tree analysis identified 2 kHz as the most important frequency for moderate-to-profound hearing loss screening in elderly people. The tree model suggested a simple two-step screening procedure in which a 42 dB HL tone at 2 kHz is presented first, followed by a 47 dB HL tone at 0.5 kHz, depending on the individual’s response to the first tone. This approach achieved an accuracy of 91.20%, a sensitivity of 95.35% and a specificity of 86.85% in the training dataset. The two-tone screening procedure provides an effective and practical method for identifying moderate-to-profound hearing loss in community-dwelling older adults.

ASCION

1. ASCION

   Mixed-signal system verification by SystemC/SystemC-AMS and HSIM-VCS in near field communication tag design

   Zhaori Bi, Wei Li, Dian Zhou, Xuan Zeng, and Sheng-Guo Wang

   In 2013 IEEE 10th International Conference on ASIC (ASCION 13), 2013

   Abs

   This paper presents a verification methodology for mixed-signal systems by combining SystemC/SystemC-AMS and HSIM-VCS verification platforms. The methodology is applied to design a Near Field Communication (NFC) tag and verify its function under certain noise conditions. SystemC-AMS is used for high-level behavioral modeling of the analog and mixed-signal components, while HSIM-VCS provides transistor-level simulation accuracy for critical circuit blocks. The combined approach enables efficient system-level verification of the NFC tag design, balancing simulation speed and accuracy across different levels of abstraction.

Thesis

1. Thesis

   Efficient and Quality Assured Techniques for Analog Circuit Design Automation

   Zhaori Bi

   2017

   Abs

   This PhD dissertation investigates efficient computational methods and quality-assurance frameworks for automating the sizing and optimization of analog integrated circuits. The work addresses core challenges in analog circuit design automation including managing process variation, improving yield estimation efficiency, and guaranteeing solution quality through novel optimization techniques tailored for the analog design domain.

2. Thesis

   Near field communication system design with a circuit implementation

   Zhaori Bi

   2013

   Abs

   This thesis presents a NFC (Near Field Communication) card/reader system design based on ISO/IEC 18092 NFCIP-1 standard with a circuit implementation. Together with functional verification of RF, digital, analog circuit blocks, the problem of power noise is also taken into consideration. The system is based on a systemC/systemC-AMS behavior model and modified to transistor level design by HSPICE/Modelsim simulation under IBM 0.13um process.